2 HN users recommended this talk1 month2016–2019score 1.5
Years with an HN recommendation, 2007–2026
Recommended in Intel ME threads as essential viewing on x86 trust and auxiliary processors.
Joanna Rutkowska's 32C3 talk asks whether trustworthy client systems can be built on x86 hardware, and what realistically can be done about the challenges, such as Intel ME.
Wow, no one here has mentioned Johanna Rutkovska's (Invisible Things Lab & QubesOS), "Intel x86 Considered Harmful"? [link] [link] Essential reading!! [this video]
Joanna Rutkowska has written a nice paper on the topic, highly recommended: [link] Edit: There's also a talk from 32c3 for those more inclined to watch a video. I am pretty worried ever since I watched that: [this video] (which is why I have researched non-Intel laptop alternatives..cliffnotes: GPUs without BLOBs are hard to find and there will be some severe tradeoffs which is expected)
The article is dated. The game changed fundamentally with the introduction of the Intel Management Engine (or the AMD Platform Security Processor) on the x86 platform. The system is now "deep pwned" as described in point 3.1.1 of the article. The manufacturer has ultimate control of the platform, the user has been disowned. [link] [this video] [link] [link]
The CSME is on the PCH[1] (when one exists). (However AMD elected to put their PSP on-die as an IP-block). It is the root of trust of the system and takes the CPU out of reset even though it's not on the CPU itself. x86-based machines have pretty much always had multiple auxiliary processors/SoCs that control various aspects of the system such as the embedded controller (a direct descendant of the 8042 keyboard controller). Another example of this is the AMD SMU which lives on the chipset and coexists with the PSP (the talk in the link gets code running on this as you described)[2]. Interestingly the Chromebook EC firmware is open source[3]. Joanna Rutkowska has done a nice overview of some of the security aspects of these topics as well[4]. Ideally there would be a standard way to verify and measure all the various firmware images (and potentially option ROMs which would be theoretically measured with SRTM via UEFI) for these system processors during boot during a DRTM event (with Intel's STM/AMD SMM supervisor enabled as well) but there is a long way to go for that. [1] [link] [2] [link] [3] [link] [4] [this video]
Overview of security aspects of auxiliary processors
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